Cortex Check - lint a Cortex-M driver for hazards that pass on the bench and fail in the field

Lint one ARM Cortex-M module in C, C++ or Rust for the hazards that work under the debugger and fail in the field, then get the review and the corrected module. Free in the browser: ISR detection (IRQ handlers, attachInterrupt, #[interrupt]), blocking calls in ISRs, FreeRTOS calls without FromISR, shared variables without volatile, static mut, 32-byte DMA alignment and cache maintenance on a cached Cortex-M7, MMIO barriers, write-1-to-clear status bits, PRIMASK nesting and long critical sections, NVIC priorities within the bits you give, Teensy 4.x, nRF52, SAMD and STM32 F7/H7 gotchas, 5 V tolerance, fault handlers, stack protection, and a timing budget with every formula; exports as .csv, .md and .json. The metered review answers every page finding in order, and the corrected module is linted again by the page. Built on the SkillSafe skill @sickn33/arm-cortex-expert, from sickn33/antigravity-awesome-skills (MIT).