KiCad Desk

Paste the KiCad schematic and board you are about to send to a fab house and work the project to order-ready in one sitting. A real S-expression reader runs free in your browser - a parenthesis inside a quoted string is not a parenthesis, and a parse failure comes back with a line and a column. On the schematic it inventories every symbol with its designator, footprint, value and sourcing fields, catches duplicate designators, unannotated parts, prefixes that disagree with the symbol, library definitions KiCad never omits, and empty Footprint properties, parses component values the six idiomatic ways engineers write them so 4k7 and 4.7k roll up as one BOM line, flags a bare 100 on a capacitor because it is 100pF to one tool and 100nF to another, and derives the wire-level netlist from wire, bus, junction, label and power-symbol geometry - calling out labels that touch no wire, power symbols on no wire, and one net carrying two names. It deliberately does NOT resolve component pin positions and says so everywhere, because a netlist that is confidently wrong at every rotated symbol is worse than no netlist. On the board it proves whether Edge.Cuts is closed endpoint by endpoint, then measures the copper layers, the narrowest track per layer, the smallest via and its annular ring, the closest pair of drilled holes, the copper-to-edge clearance, the thinnest silkscreen stroke and the smallest text, and checks every one against a selectable fab capability profile with the required and the measured number side by side - so a fail is two numbers disagreeing, never a claim the board cannot be made. With both files it cross-checks them: parts with no footprint, footprints with no symbol, footprint and value disagreements. An assembly BOM and a position file export free, in the column order an assembly house reads, with no account and no run. Then run one of four AI lanes over the same files: read them construct by construct, review the schematic and get a corrected S-expression fragment back (re-parsed in the browser before you see it), review the board layout against the profile, or check order readiness with the gates, the BOM gaps, the checklist and the cost drivers. Every lane must account for every flag the browser raised, and every designator, net and layer it cites is checked against the files you pasted. A derived work inspired by four published agent skills: @o2scale/kicad-file-format (the KiCad S-expression format for .kicad_sch and .kicad_pcb), @l3wi/eda-schematics (schematic capture and wiring), @l3wi/eda-pcb (PCB layout, routing and design rules for manufacturability) and @aklofas/jlcpcb (fabrication and assembly ordering, BOM and position files, design rules). The parser, the audits, the board measurements, the fab profiles and the exports are an independent implementation. Not affiliated with those authors, with the KiCad project, or with any board house; not KiCad's DRC or ERC, and the profile numbers are a record of published capabilities rather than a quote.

Every public app is built from a security-scanned skill and must pass a clean scan — skill and frontend — before it can be listed. Have a skill of your own? Turn it into an app — or read the step-by-step walkthrough.